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IBM v1 test

constructing a Reusable IP Platform within a gadget-on-Chip Design Framework centered in opposition t an tutorial R&D atmosphere | M2180-759 PDF Dumps and PDF Download

by using Brendan Mullane and Ciaran MacNamee,Circuits and gadget research Centre (CSRC),college of Limerick, Limerick, ireland

abstract:

A key challenge dealing with the semiconductor business is to mix intellectual Property (IP) from a considerable number of sources directly and successfully. Design times are at all times pressurized by means of time to market necessities and extending complexity. Industrial practices for constructing device-on-Chip (SoC) IP have developed beneath these pressures, but applying these practices in an educational environment gifts extra challenges. The concept for establishing a framework for producing IP became according to this reuse revolution and the merits it brings to R&D. The capacity to design high high-quality IP and to enable work practices for reuse methodology helps to obtain working SoCs in a timely and effective manner. This paper describes a strategy for implementing IP reuse practices perfect to an educational atmosphere.

1. Introduction

a number of elements are crucial for productive IP use, flexibility of integration, improved ease-of-use, minimized cost, and good work practices for constructing IP. This paper is in keeping with exact work setting up an ASIC using 0.35ìm technique expertise. The architecture in this IC is similar to SoC designs that use an 8-bit CPU and associated peripherals. it is proven that the framework for IP development established all through this undertaking can make sure successful deployment of each latest and new designs in future initiatives.

The latest trend in SoC design is to utilize existing IP as tons as viable. IP in the variety of CPUs, DSPs and controllers, are being reused in new IC projects at semiconductor systems design houses. Engineering groups now design chips with tens of millions of gates in under a yr. just recently, such productiveness would have been inconceivable, even unthinkable devoid of hardware IP reuse. Most educational environments don't have the resources and infrastructure to permit such engineering potential, besides the fact that children the underlying ideas of reuse can be applied to permit extra advantageous IP technology and potential retention for constructive R&D.

This paper introduces a collection of instructions and a methodology used to make sure a constant method to designing IP and to permit for reuse of these modules in future initiatives. the primary stage changed into to investigate most useful industrial observe. Work describing the ASIC development cycle and its affect on IP technology became conducted. a group of requirements for guaranteeing IP high-quality and ease of integration was additionally prepared. A key goal changed into to make sure capabilities may be retained in the college centre to have in mind expected graduate turnover.

2. IP Reuse Framework in CSRC

A evaluation of the usual issues in design use and reuse was initiated [1]. a lot of IP standards were reviewed and these included Freescale’s Semiconductor Reuse ordinary [2], VSI Alliance’s set of specifications for establishing SoCs [3] and OpenMORE [4]. IP reuse could not ever have took place with out necessities or devoid of the underlying infrastructure [5]. Design and verification reuse, a truth of existence these days for most SoC designs, ensures the productiveness hole is kept manageable[6]. Design reuse regarded a simple idea that can be comfortably adopted, has persisted to be problematic in observe. problems exist in getting engineers to have confidence that reusable IP will work every time it's used in an IC. presenting IP support functions and adoption of a correct verification system develops this have confidence.

2.1 SoC architecture and Infrastructure

The purpose of this project became to set up a design methodology for generating IP. The methodology involved architectural decisions and selection of design-flows for IP development accompanied by the prerequisite IC design equipment. task criteria such as the SoC architecture, third-birthday celebration core use, in-residence IP development and the gadget bus interface had been all regarded earlier than the IC architecture turned into concluded and the peripheral integration became conducted. The basic SoC architectural diagram is proven in figure 1 and the finished chip became taken through verification and the returned-end levels of synthesis, layout, static timing analysis and ultimate design rule checking.

figure 1: SoC Design structure

here key selections have been made in the case of the IP aid constitution.

2.1.1 Peripheral Bus Interface

The alternative of a common SoC device bus for connecting the CPU to the device peripherals was critical to the pursuits of this mission. the use of a standardized bus architecture is essential to constructing reusable IP. a number of bus specifications had been investigated for the wants of the CSRC IC initiatives. The 8051 CPU became used in this design and besides the fact that children the interior particular characteristic Register (SFR) bus become regarded, the authors wished to employ a standard bus design to be reused in other IC implementations.

most of the essential IC and IP groups base their IP portfolio construction round a single SoC bus architecture. Semiconductor groups comparable to ARM and LSI good judgment use the open supply AMBATM [7] bus normal. IBM makes use of its personal proprietary CoreConnectTM [8] bus average. The OpenCores initiative makes use of the WishboneTM [9] described bus interface. The authors observed that the AMBA bus structure changed into smartly supported amongst the IP vendor community. This vast acceptance arises from the supply of an open bus commonplace it truly is license free and smartly confirmed in present SoC designs. purchasers have a excessive diploma of self assurance choosing IP it is considered seller independent. additionally, the AMBA bus is neatly supported by EDA corporations providing verification aid. The AMBA bus became chosen as the bus interface for CSRC SoC projects for these reasons.

The AMBA bus allows for partitioning for modular designs[10]. Its methodology for embedded processor design encourages both a modular and first time correct gadget design. It also accelerates product migration by means of aiding module reuse. In specific, the AMBA APB bus specifies a versatile interface and small overhead support for low bandwidth peripherals. The IP design using the AMBA interface is made less difficult by way of partitioning the high-end and low-conclusion devices within the equipment and supports energy effective designs. all of the peripherals during this design used the AMBA - superior Peripheral Bus (APB) because the standardized interface. The CPU as a single bus master became interfaced to the entire peripherals by way of an in-house designed AMBA bridge interface.

The benefits of the use of a common bus interface for core building are neatly documented [1, 10, 11]. A pattern AMBA APB register module, shown in determine 2, turned into constructive for demonstrating the desired interface design to postgraduates. The RTL code for this module helped the team to keep in mind the concepts of decent coding practice to consist of parameterization and established using revision manage for code alterations and bug fixes. all of the IP developed during this IC challenge may also be reused in another AMBA primarily based SoC purposes and this aids future product and platform building

determine 2: pattern APB module

2.1.2 third celebration Core Licensing

a different gigantic task was to designate an appropriate microcontroller for the undertaking. The IP community became approached in regards to licensing of the CPU and debug cores. there have been a couple of elements to licensing IP cores from an tutorial viewpoint. It was standard to be sure a licensing association was made the usage of a non-business research- licensing mannequin. Many carriers were only prepared to license their cores in line with a full commercial association and the prices quoted have been beyond an tutorial research price range. Some providers had been willing to accept as true with a reduced non-business license fee with the re-introduction of full fees offered the IC proceeds to commercial software. different IP carriers confined their set of deliverables to FPGA netlist implementation best. This restrained their option of third party CPU and debug cores. fortunately, some IP corporations had adventure coping with tutorial cases and were prepared to liberate IP deliverables and support for non-industrial analysis undertaking at a decreased charge. The leading writer become in a position to perform a survey of relevant cores and came to an settlement for the 3rd birthday party IP crucial for the SoC assignment.

2.1.three Design Flows

The ASIC design movement and electronic Design Automation (EDA) device option is an important element of a good IP framework. The alternative of equipment have to complement the design flows and assist reusability of IP. The centre accesses device units provided as educational programmes from the semiconductor EDA businesses. The CSRC additionally has access to established EDA tools via the Europractice[12] application carrier scheme. Their FPGA and Digital design flows have been drawn up across the availability of these equipment and to plan the SoC IP building and integration. These flows have been helpful in picking the different levels concerned within the building of IP and SoC designs. in addition to the digital design stream, a stream for FPGA prototyping turned into additionally delivered. The FPGA building allows for for an affordable design validation platform and adds confidence by using ensuring appropriate conduct earlier than final tape-out.

2.1.three.1 Digital IC Design movement

The digital design follows the classic ASIC implementation route. a number of semiconductor business sites and technical paper searches printed the standard design stream that exists for digital ASIC design [13], [14].

figure three: Digital IC design stream

The design flow and tools alternative as drawn up in determine three were adapted to tool availability and the alternative of IC approaches provided with the aid of Europractice.

2.1.3.2 FPGA Design flow

The FPGA stream in determine 4 is very similar to the digital IC design flow, however the design equipment to implement and program a FPGA design are distinct. The project used the Xilinx design kits and tools made purchasable by way of the Xilinx institution Programme. They used Xilinx Spartan 2 and three boards to enforce the digital design aspects. The Xilinx ISE webpack is a collection of equipment that takes Verilog RTL code and runs it via synthesis, real design to machine configuration. The remaining bit file can then be downloaded to software the FPGA gadget to examine the practical conduct of the digital design. FPGA verification options and their significance in design validation and reuse are discussed later.

determine 4: FPGA Design stream

2.2 CAD Infrastructure

The CAD infrastructure turned into greater to carry out SoC building in the centre. The original structure protected three low-grade UNIX servers for running the IC design equipment and conserving task statistics. A plan turned into initiated to Boost the IT hardware wants. each and every of the person PCs were put in with VMware Linux, permitting users to preserve their home windows OS but more importantly each notebook could use its personal CPU processing energy with Linux to convey enhanced performance. Two high vigor Linux mainframes, obtained for keeping the task databases were also utilized as license servers for the supported EDA tools. the brand new set-up offers the performance necessities to carry out IC R&D in the CSRC centre.

a further step became identifying the EDA tools indispensable for IP development. equipment for verification and ensuring pleasant of RTL code were now not in place. despite the fact using their Europractice membership, the centre had access to familiar EDA tools at a reduced can charge. equipment akin to ModelSim for RTL verification and Leda for RTL evaluation were acquired. The latest version of Design Compiler became also upgraded in accordance with trade requirements.

3. Design Methodology and IP reuse Implementation

application of reuse can pay off in terms of building cost and time-to-market. This area summarizes the development milestones for a customary IP design. Defining the circulation and associated design stories helps certain a repeatable, excessive quality, and reusable block of peripheral IP. yet another advantage of a documented flow is that different design companies can use this methodology to enhance IP in an identical method; guaranteeing IP is constant in its implementation, integration move, deliverables, and standard pleasant.

three.1 construction Milestones

IP/SoC design milestones are important to the beginning of working silicon and achieving a ‘correct first time’ policy. These milestones are markers positioned down right through the building section to manage and measure the design endeavor and development. These markers indicate stories taking place all through the critical tiers of the design phase from start to end. Milestones take vicinity on the herbal progression of the undertaking. figure 5 and desk 1 describe the sign-off milestones to include all predominant design studies.

determine 5: IP construction Milestones

table 1: IP development degrees

stageReview Description FSR purposeful Spec assessment practical specification is comprehensive, details on effort estimation, work breakdown constitution and schedule. DSR Design delivery evaluate Design beginning, practicing, RTL coding & synthesis guidelinesTPR test Plan evaluation comprehensive specification of verification environment, verify cases, bus-fashions, transactors. RCR RTL Code evaluation RTL worm fixes identified through exhaustive verification & RTL Lint/code checking TLR Trial design assessment set up floorplan and operate P&R. Floorplan according to module connectivity, get to the bottom of congestion and timing –study clocking FVR ultimate Verification review high priority trying out accomplished. general bugs in the RTL are mounted. coverage analyzed. Low precedence checking out adequate. FDR final Design assessment review integrity tests (DRC, LVS) STA, examine Vectors and closing gate-degree verification with comprehensive design timing.

3.2 assignment Database structure

A standardized listing constitution is a must-have for IP reusability. a good and simple to use database constitution ensures compatibility and consistency of peripheral design. IP development comprises specification, coding and verification as key design ranges. subsequently, many help file codecs are required. IP maintenance is additionally a key concept in IP reuse. The means to log and keep song of design changes is vital to the basic fine of the design. determine 6 shows the CSRC listing structure to guide the IP development degrees.

figure 6: commonplace CSRC directory Database

three.3. Reuse guidelines

3.3.1 Specification studies

The design reports are significant in terms of generating a framework for IP construction and reuse. These studies support documentation and confirm decent design practices.

three.3.2 functional Specification

This document offers a detailed practical description of the module and is written prior to the IP construction. The FSR overview takes region to be sure all aspects of the peripheral performance are lined. The specification could be used to beginning the design and RTL coding. The practical specification needs to be up-to-date thus with any extra facets necessities. The CSRC makes use of a draft template document as a guideline for generating purposeful block and IC design requirements.

3.3.three RTL Coding and analysis

RTL construction contains coding the peripheral in a hardware description language akin to Verilog or VHDL. Verilog RTL become used and a group of coding guidelines for the IP generation become issued. This set of coding principles ensures consistency, coding trend excellent and provides for greater maintenance. The RCR is a high degree evaluation of the RTL code to be certain it is stylistically appropriate and maintainable. The intent is to double-investigate the code best. The groundwork for this review is the RCR guidelines. RTL evaluation is performed the use of Leda for crosschecking RTL code guidelines towards the Reuse Methodology guide (RMM). initial FPGA/IC synthesis can also be used to highlight any RTL concerns with regard to synthesis.

three.3.4 Revision handle

Revision handle is indispensable to the theory of design reuse and ensures vital suggestions is not misplaced throughout the design part. Revision manage and file administration is above all critical all through RTL coding as any code lost all through this stage can significantly affect the universal design timeline. To support manipulate files, engineers use source control management programs. These are typically bundled with the Linux operating systems or obtainable from GNU (RCS, CVS, Subversion). These code administration techniques provide an entire heritage of each file as separate types.

three.3.5 computer virus preservation

dealing with bugs is a vital consideration for any design framework. it's normal to locate functional irregularities in the design and their prevalence doesn't replicate the expertise of hardware designers. once an issue is recognized, it needs to be resolved. All design groups want a technique for tracking considerations and making certain their decision. The authors proposed protecting a worm record for any design related concerns.

three.4 Verification and Validation environment

The verification part is essential to offering first time working silicon. Their verification methodology uses a twin song approach. Verification happens at the module level and also on the SoC equipment degree. The Module Verification environment (MVE) functionally validates the core and ensures all design characteristics were comprehensively established. The SoC Verification atmosphere (SVE) exams the cores’ behavior on the system stage and in specific exams the connectivity between the core interfaces. An FPGA/ASIC design verification method turned into used to validate the project at the device SoC level.

3.4.1 Module Verification environment (MVE)

a necessary part of the MVE turned into the era of the APB Bus practical mannequin (BFM) to generate the practical conduct of the system bus. all the peripherals have been in keeping with this standardized bus structure and this enabled using a frequent model to test the bus interface and registers contained in the peripherals. This model extra supplied a straightforward to use check ambiance. The diagram in figure 7 illustrates this. The BFM utilized Verilog tasks for read/write accesses, including wait state control and turned into reused in all of the peripheral examine environments. The BFM become valuable for working tests to obtain self belief in the useful habits and for concentrated on high code insurance.

determine 7: APB Bus useful mannequin

3.four.2 SoC Verification ambiance (SVE)

The SVE consisted of a separate but an identical examine solution for FPGA prototyping and the ASIC equipment level verification. The FPGA solution turned into effective for mapping the comprehensive SoC RTL code to include the CPU, debugger and all of the peripherals onto a FPGA. determine 8 illustrates the simple architecture implemented onto the FPGA machine.

figure 8: FPGA Prototype Validation

The CPU and other leading peripherals are connected together as a single platform and assessments have been developed in R8051 CPU core software code to operate the peripheral checks. The ASIC verification atmosphere is comparable to the FPGA check mattress, apart from in this case all assessments were run the usage of RTL and system certain gate-degree stimulations. each of the peripheral firmware checks developed for the FPGA prototyping were reused at ASIC system stage.

4. consequences and Conclusions

The task aim became to enforce a SoC design framework for the delivery of reusable IP. The chosen commonplace system bus aided the building of plug and play peripherals that will also be reused in many different SoC purposes. The building of the 8051 CPU exterior records bus to device bus-bridge supplied for a standardized interface and simplified the peripheral construction.

The design flows of Figures 4 and 5 were adopted to be certain a constant design strategy for the development and equivalent help for trade common EDA equipment. The listing constitution as explained in part three.2 became also important for associating data with each and every stage of the IC building and holding a well-managed database. each and every of the implemented IP blocks follows this popular database structure and this ensures reusability going ahead. Design stories ensured self assurance and high-quality of the IP block design. The Verilog code become reviewed to make certain revision manage and RTL coding instructions were adhered to. an identical evaluation changed into performed to make certain the verification environments at module and system stage have been applicable to look at various the performance of these designs. The RTL was validated on a FPGA equipment and tests had been performed on the gadget level to check the peripherals linked to the 8051 CPU.

The IP framework as discussed in this paper is appropriate for implementation in an educational centre wishing to perform a reusable IP programme. this technique and reuse innovations are standard in industry, but because of funding and aid constraints, might also now not all the time be easy to install in an educational environment. This paper discusses the implementation of IP development for decrease bandwidth peripherals; nonetheless the underlying ideas of IP use and reuse are the equal.

4.1 tutorial Centre Specifics

group of workers necessities for analysis are sooner or later resourced from graduates pursing MEng and PhD levels. in the CSRC, group of workers and educational researchers are accountable for main initiatives and mentoring college students. The graduates need skills building to deliver them up to velocity and having a structured construction methodology enables deliverables to be met in a timely vogue. The merits of IP knowledge retention became another reason for introducing the IP development framework, as work generated on projects carried out in the past would had been complicated to growth as soon as postgraduates had achieved their analysis degrees. This turned into a vital problem to resolve, as advantageous venture work conducted in the past might also had been unnecessarily lost.

four.2. Future concepts

The cores may well be further enhanced through featuring a device C or C mannequin as a part of the developmental degrees to extra the stage of abstraction and to speed up design verification and software building.

SystemVerilog is a hardware design and verification language with superior aspects meant to assist users increase reusable, transaction-stage, coverage-driven testbenches. options corresponding to fact based mostly Verification (ABV) may well be applied to the bus protocol to video display pin undertaking and the application of insurance-pushed exams add confidence in working silicon and supply an exhaustive testing environment. These aspects introduce concepts of verification reuse.

Design for examine (DfT) is often excluded from the design circulate in an educational atmosphere. DfT is a extremely crucial function vital for IP reuse. The IEEE 1500 common for Embedded Core look at various (SECT) specifies a core wrapper design to accommodate DfT features. This IEEE 1500 compliant wrapper design might provide a useful extension to the existing IP building stages.

5. Acknowledgements

The authors well known the support of the Circuits and systems research Centre (CSRC) within the digital and laptop Engineering (ECE) Dept. at the school of Limerick.

6. References

[1] Australian Microelectronics community, "IP design and Re-use," Jun, 2005.

[2] Freescale Semiconductor, "Semiconductor Reuse average v3.2," Feb, 2005.

[3] VSIA Alliance, "VSIA structure document v1.0," Mar, 1997.

[4] P. Bricard, Jean-Pierre Gukguen, "making use of the OpenMORE assessment application for IP Cores," in ISQED 2000: Synopsys, Mentor portraits, March, 2000.

[5] J. Shandle, G. Martin, "Making embedded utility reusable for SoCs," EETimes, Jan, 2002.

[6] J. Bergeron, "Writing Testbenches - functional Verificaton of HDL models", Kluwer academic Publishers, 2003.

[7] ARM, "AMBA™ Specification (Rev 2.0)," ARM LTD, may 1999.

[8] IBM. CoreConnect Bus. architecture, "http://www-03.ibm.com/chips/items/coreconnect/."

[9] R. Herveille, "WISHBONE device-on-Chip (SoC) Interconnection structure for portable IP Cores," OpenCores organization, Sep, 2002.

[10] D. Flynn, "AMBA: Enabling Reusable On-Chip Designs," IEEE Micro, vol. 17, 1997.

[11] M. Kaskowitz, "flexible, necessities-based mostly IP key," EETimes, Dec, 2002.

[12] Europractice, "http://www.msc.rl.ac.uk/europractice,"

[13] QualCore good judgment, "QualCore SoC movement."

[14] V. P. Nelson, "VLSI/FPGA Design and test CAD tool flow in Mentor graphics," Feb 15, 2006.


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