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Foundry FN0-125 : Foundry Networks Certified Network Engineer (FNCNE) Exam

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excessive efficiency Connectivity IP -- keeping off Pitfalls When deciding on An IP seller | FN0-125 dumps collection and exam Questions

by way of Navraj S. Nandra SynopsysMountain View, California united states of america

summary:

The demand for connectivity IP for top velocity serial busses reminiscent of USB 2.0, PCI categorical®, SATA, DDR2 and HDMI is expanding as ordinary interfaces in applications comparable to single chip recordable DVD CODEC’s and MP3 avid gamers. in order to stretch battery life of these chips, the semiconductor technologies require extremely-low vigor derivatives of excessive-performance good judgment manufacturing strategies, enabling production of very low-vigour chips for these cell platforms and small-kind component instruments. these days a lot of these chips are manufactured in 90 nm, and the ramp for sixty five nm design starts has been greater aggressive than anticipated. forty five nm is following close behind, with early models of design guidelines and technique parameters already available. on the grounds that connectivity IP requires both a digital controller (MAC) and blended-sign circuitry (PHY), the problem is to meet analog efficiency in a know-how that has been focused for densely packed digital good judgment.

IP is the critical enabler to satisfy the time to market demands for these SoC’s and an industry of IP providers has mushroomed to service this demand. the important thing question for the SoC developer, and the purpose of this paper, is to spotlight the importance of choosing the correct IP seller – a way to evade the pitfalls.

in this paper, they are able to discuss how to choose a third birthday party IP seller, the way to investigate third celebration IP, and a few of the gotcha's when integrating third birthday party IP, with a distinct focus on the SerDes-primarily based PHYs for PCI categorical and SATA as well as PHYs for USB and DDR2. moreover, they can discuss the have an effect on of 65 nm and forty five nm method results on yield, they will evaluation the advantages and disadvantages of relocating to serial hyperlinks, they are able to suggest comprehensive vertical built-in solutions, and they are able to current production checking out ideas.

as the variety of third celebration IP carriers enhance, the great of the IP purchasable varies. This paper discusses IP preference criteria to ensure that the appropriate selections are made.

determine 1 highlights the standard elements of IP option, when it comes to functional correctness, integration, usability and support.

determine 1 primary elements of IP option

obviously, the IP should be correct functionally, however different factors are essential akin to ease of integration and support via experienced protocol consultants – with design teams determined world-large, the IP dealer should be capable of supply this aid circular-the-clock, each day.

1.0 The Gotcha’s – The Ten Questions

determine 1 described a excessive-level view of IP vendor option, but as a result of the complicated nature of connectivity IP, additional investigation is required. right here are the ten most important concerns:

  • How mature is the IP being sold? Has this IP taped-out in silicon? What method and foundry?

  • Or, if the IP is mature, what number of clients are shipping ICs using this IP?

  • Does the IP design group have high-speed design experience the use of deep sub-micron CMOS technologies with low deliver voltages?

  • Are there any valued clientele that have used or at the moment are the usage of this IP? if so, are you able to contact them for reference and to discover if there have been any serious issues with the IP?

  • How became this IP verified? Has it been certified by any unbiased necessities or compliance physique?

  • What are the latest errata?  Is there a plan to repair the latest bugs? what's the dealer’s willingness to share such errata?

  • what is the supplier’s tune checklist within the business?

  • What stage of assist is the IP dealer willing to supply? Is the seller inclined to offer functions to customise the IP for the utility?

  • What degree of integration assist is required? Are there any particular system alternate options required, as an instance deep NWELL, thick metal for inductors, MiM capacitors or varactors?

  • Has the IP been tested for ESD and latch-up robustness? Are ESD instructions supplied?

  • until the IP being purchased is mature, it might probably comprise bugs. as a result of the more and more advanced nature of IP, earlier than any buy is made, the 1st step in doing due diligence on third birthday celebration IP is to verify the have an impact on of the present bugs (and every other errata) on the supposed application. Some bugs may additionally only be latest when specific facets or configurations are enabled. If the bugs do have an effect on the meant application, it is vital to get a written dedication and time table for their correction.figure 2 suggests the seven layer OSI mannequin. For connectivity IP, this is divided into levels L1 to L4. Ideally, an interface standard (e.g., USB and PCI categorical) IP vendor may still deliver a complete answer including all of these, pretty much circumventing interoperability concerns.

    determine 2 Seven layer OSI model

    The 2d step in the procedure is to examine how completely the IP turned into established. For mature IP (which has passed through distinctive a hit tape-outs), this effort is minimal. despite the fact, for brand new or rising IP, the certification and verification effort can also be difficult. This effort is always underestimated by means of the SoC implementer, and in some instances unnoticed via the IP dealer. The key's to be sure that the IP has passed through a certification manner, for instance with PCIe SIG.

    The third step is to get written dedication from the dealer on concerns that you simply may additionally locate throughout product construction and IP integration.

    The subsequent section discusses the above challenges in the context of the widely used and rising IP.

    2.0 high speed Serial hyperlinks

    lately, excessive-speed serial links have develop into increasingly common area in the industry. There are a couple of merits to the use of excessive-speed serial hyperlinks as a substitute of supply-synchronous parallel I/O at present deployed. because of their merits, the industry could be moving towards high-velocity serial links for these applications the place efficiency, footprint, and cost are paramount. The regular protocols are the SerDes primarily based (serializer-deserializer) PHY’s for PCI express and SATA. determine three clearly shows the potential of the usage of the serial based approach in comparison to the parallel cable.

    determine three ATA cable (under) and SATA cable

    2.1 high velocity Serial link merits    

    right here summarizes the advantages of serial links.

  • No setup/dangle necessities on data lines. as a result of both statistics and clock are embedded in the same differential pair, this simplifies routing on a broadcast circuit board. For parallel I/O, the clock and records pins have to be routed in order that all facts lanes meet the setup and grasp requirements of the supply synchronous clock.

  • less pins required. To achieve the equal performance as a single PCI categorical link, a similar parallel interface would deserve to run at 250 MHz with eight statistics and 1 clock pins compared to simply 2 pins for a serial hyperlink.

  • more desirable bandwidth per pin. This minimized the number of pins required and number of traces on the published circuit board (PCB). Minimizing I/O allows for using a cheaper kit with a smaller footprint. using a less expensive equipment lowers standard ASIC cost. additionally, through the use of a smaller footprint, the published circuit board cost is minimized as well.

  • excessive-velocity. A single PCI categorical hyperlink gives 2.5 Gbps bandwidth while even the high-speed Pentium four front side Bus (FSB) runs at a optimum of best 1066 MHz. (Future PCI categorical device will guide 5 Gbps bandwidth)

  • 2.2 high velocity Serial link dangers

    There are some risks and these should be discussed with the IP dealer.

  • Debug is greater elaborate considering the fact that a common logic analyzer can't without problems hook up to a excessive-velocity serial hyperlink. costly oscilloscopes may well be obligatory to debug sign integrity issues.
  • design of a serial link is advanced because of the should take a look at routing and termination requirements for the differential pair.
  • 2.3 identifying Serial link IP

    as with every new technology, the alternate-offs between constructing the excessive-speed serial link interface internally or licensing the IP via a third party deserve to be fully examined.

    The excessive pace serial hyperlink contains two layers: the physical layer (PHY) and the media-entry layer (MAC). The PHY is responsible for merging gradual incoming information (sixteen bits at 125 MHz for PCI specific) and clock (125 MHz for PCI specific) and producing two differential excessive-velocity outputs (2.5 Gbps). The PHY is additionally liable for decoding the incoming high-velocity serial data move. The MAC handles all high-level performance, comparable to circulate control, transaction technology, routing, and so forth. In PCI express and SATA, the MAC layer includes the transaction layer and the statistics hyperlink layer.

    figure 4 PCI categorical, finished answer

    considering the fact that the PCI express and SATA PHY’s are advanced (involving excessive-velocity analog/combined-sign design), it's usually licensed from a 3rd celebration. Few companies are in a position to constructing the PHY internally or in sufficient time.

    The MAC can either be developed internally or licensed as smartly. this may generally depend upon the time to market requirements, availability if proper IP, and verification requirements. For PCI express and SATA, with strict necessities in compatibility, verification, and trying out, the building time for the MAC layer may also be reasonably lengthy. for that reason, licensing the MAC as smartly because the PHY makes feel.

    When licensing each the PHY and MAC layers from the same third party, both layers may still have been proven together. it is important to understand what configurations were established collectively and what strategies of verification had been utilized. figure four PCI specific, complete solution shows the PCI express complete answer with numerous configurations of MAC that can be found and also the verification IP.

    If both layers are licensed from two distinctive vendors, then the verification challenge is a lot more suitable. for example, in PCI categorical, nearly all of PHY and MAC layers communicate to each different over the PIPE interface (as defined by using Intel). besides the fact that children PIPE is a typical, it can be interpreted differently by distinct providers. in addition, low-power functionality isn't very obviously distinct. These considerations can lead to bugs. consequently, it is terribly vital to bear in mind not handiest the PIPE interface spec – but the implementation assumptions made by way of each vendors.

    three.0 My Chip needs USB 2.0

    just about all cellular contraptions require USB performance and in addition to the points made above the goal for USB is to be low in vigour and enviornment. therefore the IP seller ought to supply a core it really is competitive in enviornment and power without sacrificing performance.

    gigantic enviornment reduction will also be completed via a combination of architectural and implementation optimizations. as an instance, the PLL/DLL structure should still be targeted to assist the 12/24/48 MHz reference frequencies with 480 Mbs output. also products requiring USB IP tend to comply with the aggressive function measurement rate reductions and for this reason the PHY should be ground-planned in such a way that because the digital block scales with the smaller technique geometries, allowing the overall macro area to reduce -- here's no longer at all times the case with analog/blended-signal designs.an extra crucial consideration is the pin count design – low pin count is an enormous capabilities when it comes to enabling the use of lessen-charge packaging. The need for fewer pins additionally reduces the charge of construction check, in addition to considerably easing SoC integration.

    With the transition from ninety nm to sixty five nm and forty five nm method geometries, yield has assumed a tons better precedence. With USB, chip yield is linked to the performance of key specification parameters, corresponding to PLL jitter efficiency and band-hole variation, in addition to being dependent on chip enviornment. A decrease chip yield, even with the aid of as little as two or three per cent, can cause manufacturing can charge increases which can also overwhelm any discount rates that are carried out with a smaller die area.

    4.0 Why may still I Ask For an entire DDR2 memory Interface answer?

    The merits of high performance DDR2 SDRAM recollections require techniques-on-chip (SoC) interface designers to approach reminiscence subsystem integration with attention to element. As data rates have regularly improved from DDR2 four hundred, DDR2 533, DDR2 667, and now DDR2 800, the complexities linked to the timing and signal integrity of the reminiscence interface has turn into expanding intricate.

    Migrating from 400 Mbps to 800 Mbps DDR2 requires additional engineering effort. Ideally, this migration become planned for when the 400 Mbps software became first applied. For DDR signaling, expanding frequency reduces complete bit time from 2.5 ns to 1.25 ns. This bit time is then evenly divided right into a setup-and-grasp funds of 625 ps each and every. supply synchronous timing depends on the uncertainty of the location of the DQ records side relative to the DQS strobe edge. Any skew, jitter or uncertainty component will erode the setup and grasp margins.

    total timing consists of three budgets: Transmitter, Interconnect, and Receiver. Nominally, each and every of these three budgets account for about 33% of the overall timing price range. JEDEC managed to lessen the DRAM contributors to the transmitter funds (throughout Reads) and the receiver budget (during Writes) accordingly with the enhance in frequency. alas, the scaling is not utilized proportional to the bit duration as information charges enhance. for example, the uncertainty of when the DRAM will generate DQS relative to CK is +/- tDQSCK. For DDR2 400, here is +/- 500 ps, or forty% of the 2500 ps bit time. For DDR2 800, here is +/- 350ps, or fifty six% of the 1250 ps bit time. assume additionally, that the system dressmaker planned for this migration and certain the controller, PHY, and i/O phone to fulfill 800 Mbps timing originally of the challenge. The ultimate timing budget is consumed via the interconnect between the PHY and the DRAM. Three objects in certain in the interconnect finances deserve to be addressed.

    4.1 PCB and package Skew

    The electrical length differences between the DQS and the DQ of a particular byte must be decreased to fulfill the now reduced timing finances. the place a 35 ps skew budget may additionally have been enough for four hundred Mbps, below 20 ps can be required at 800 Mbps.

    four.2 Inter-image Interference (ISI)

    This impact is the overlap of random signal bits at the receiver. ISI is exacerbated by means of capacitive loading of the net and frequency dependent losses in the channel routing. The have an effect on is to enhance the facts-dependent jitter on the receiver thresholds and reduce the minimal amplitude of the received sign. both of those effects can also be captured in eye-patterns. When the bit fee doubles, these effects will increase on the grounds that the signal now has 50% much less time to reach the mandatory threshold degrees. DDR2 has lower AC thresholds at 800 Mbps that addresses the amplitude subject; youngsters, accelerated data-stylish jitter will nevertheless be a problem.

    happily, the capacitive loading will also be decreased with the aid of reducing the variety of ranks of reminiscence of each DQ and DQS, in consequence decreasing the roll-off of the received sign and decreasing ISI. The PCB losses can be reduced through shortening the standard route length, the use of a decrease loss dielectric fabric and/ or increasing the hint width (be careful for crosstalk).

    4.3 SSO pushout

    right through write operations, the DQS is launched 90 degrees out of phase with the eight DQ indicators of the byte. When the eight DQ traces toggle simultaneously, the ensuing latest draw in the course of the kit wire inductance could cause the vigor rail to crumple, resulting in a extend of the output of the DQ signals. This “push out” will subtract from the attainable install time budget. If nothing is achieved, when the bit price doubles, the percentage of the finances occupied by SSO push out will additionally double. To cut back the contribution of SSO, the kit wire inductance ought to be decreased. This can also be finished by way of switching from bond wire to flip chip or expanding the number of energy/floor pairs in the interface. other less useful measures would be using double bonds on power and ground, or including decoupling. Decoupling is most constructive when on-die. Decoupling can also be positioned close to the die on the pad ring, in the package or floor-set up to the equipment. including capacitance on the PCB will probably have too a whole lot positive inductance to correctly decouple high-frequency vigour/ground noise. Any of these solutions boost the cost; for this reason, the architect may still plan for 800 Mbps operation from the beginning.

    Planning is the important thing. When designing for 400 Mbps, expect what should be required to get to 800 Mbps and encompass it on the front conclusion.

    To summarize there are two options:

    customer assembled package – requires meeting

  • particular person I/O, DLL, PLL’s and glue good judgment
  • gadget efficiency uncertainty
  • excessive-velocity common sense/equipment integrator required
  • completely-assembled DDR2 memory PHY macro
  • constructed-in margin within the design
  • increased sure bet of device performance
  • in the reduction of possibility and development time
  • excessive speed common sense/equipment integrator now not required
  • 5.0 The have an effect on Of 65 nm And 45 nm On Yield

    In today’s deep sub-micron technologies the following effects impact yield and have to be eradicated.

  • STI – Shallow trench isolation - this is a fabrication method used to isolate energetic areas and can trigger currents to be distinctive from simulation and it depends upon transistor region.

  • NBTI – bad bias thermal instability - degrades PMOS gadgets steadily over time ultimately via an increase in the threshold voltage and reduction in mobility as a result of bad gate bias and/or higher temperatures constantly round one hundred+C. The internet impact is that the PMOS current pressure is degraded over time and this can induce timing disasters in digital circuits.

  • Matched devices, like present mirrors and differential pairs, that are asymmetrically stressed may have an additional mismatch element, apart from mismatch from processing diversifications, inflicting additional efficiency degradation to the device.

  • HCI – scorching carrier injection - degrades the efficiency of NMOS devices in an analogous means however via a unique physical mechanism to NBTI. in contrast to NBTI, HCI is a feature of the electric box throughout the channel (i.e. from drain to source) whereas NBTI degradation is a feature of the field across the oxide.

  • Circuit design have to be in a position to accommodate smartly proximity consequences.

  • Electro-migration assessments for abilities short circumstances need to be made. this can occur on dense arrays of conducting thin-film metal conductors, and over time, high latest densities trigger these conductors to fail causing steel separation.

  • also, there may still be checks for satisfactory metallic widths and tests for metal / MOS / POLY / via / contacts.

  • These results do have a significant affect on the design of the analog/blended-sign portions of the connectivity IP and the supplier need to have deep skills in knowing these consequences. 6.0 IP testing & Verification

    Thorough validation of IP involves two phases: pre-silicon and put up-silicon verification. For pre-silicon verification, the following steps could be integral:

  • vendor IP verification - run dealer’s provided verify vectors to determine the IP. here's continually performed at Verilog/VHDL RTL stage and verifies that the IP delivered is functional. Synthesis can also be executed at this time as well, to investigate for any synthesis considerations.

  • seller IP certification – the usage of in-condominium or externally bought look at various vectors and look at various benches, to check the great of the IP purchased by means of running a test suite. This unbiased certification may locate considerations on the IP itself that may additionally have been ignored by dealer’s own test vectors. this is peculiarly vital for applied sciences which aren't mature or for IP with restrained silicon tape-outs.

  • supplier IP integration – the use of in-condominium vectors, assess the usage mannequin of the IP. however the IP can be defect-free, it could be hooked up incorrectly or utilized in techniques for which it turned into no longer intended. as a result, it is awfully essential to have adequate test cases and look at various benches to utterly pastime all the usage modes of the third party IP.

  • FPGA verification platform – if possible, map the total (or subset) design to an FPGA and investigate the IP on a construction board. Many FPGAs currently exist which support high speed serial links (Xilinx). in addition, there are off the shelf building structures attainable (Dini) which will also be purchased to speed up this building. This platform may also be used to investigate the MAC layer and speed-up application driver building.

  • Hardware acceleration platform – if entry to hardware acceleration is obtainable, it could be fairly a good option to determine the design and get a head delivery on software driver construction. Bugs are an awful lot more convenient to determine and correct in a hardware acceleration atmosphere than in a FPGA environment.

  • figure 5 The bought eye for PCI categorical - On board diagnostics

    For post-silicon verification, here steps are integral:

  • Serial I/O trying out – for top-speed serial hyperlinks, (together with USB and DDR2) particular checking out equipment, including excessive-pace oscilloscopes may well be integral to investigate that the excellent of the PHY electrical signaling. These can be able to measure the attention-diagram, jitter, and different electrical parameters quintessential for serial link certification. Having visibility into the acquired eye as proven in figure 5 is a really beneficial capability to show the link performance. This eye-diagram become taken by the use of the JTAG port and considered on a laptop – without using any test gadget.

  • MAC Verification – to fully activity the media access layer, a couple of stand-alone structures can be found from Catalyst and Agere. These systems send selected verify patterns to the equipment beneath look at various (DUT) and predict a selected response. These can be used to identify MAC compatibility and certification issues, in the illustration of PCI specific, before going to PCI-SIG or any other certification physique.

  • 7.0 From The look at various Engineer’s viewpoint
  • The SoC designers do not design the IP and therefore cannot add look at various points. in the event that they can not simulate it with a verify bench, they cannot verify it.

  • SoC test engineers always have vectors they flow in/out from simulation. All analog exams need to be hand coded.

  • test engineers need to devise tests to get ideal analog fault insurance. The designers don't know an awful lot concerning the analog component of the IP.

  • Most analog exams require external hardware to accurately check. constructing this hardware takes time.

  • the first time test vectors/code are Checked on real silicon is when the SoC comes back.

    So how does the verify engineer comprise the PCI express compliance eye-masks into the ATE without altering the signal? He definitely can't hold a excessive pace tester on each pin. The check engineer’s situation is that with the primary flow/fail look at various of the external loop-lower back strategy he will no longer understand how an awful lot margin he has – chips that move the loop returned test which are marginal may additionally fail over time when subjected to real world circumstances. Referring again to determine 5, the usage of voltage and section margining the link may also be reliably validated in a construction verify environment. These limits are set by using simple enter and evaluate vectors which are offered with the IP. A comparison of this method with the general formula is outlined in table 1.

    desk 1 excessive velocity SerDes checking out comparison

    8.0 Conclusions

    This paper reviewed in aspect the crucial concerns for opting for an IP seller. the important thing considerations can be summarized as:

  • as a way to be successful the IP supplier must have a song list of customer wins and silicon success.

  • The seller should still offer an entire answer: MAC, PHY and verification IP. These should still interoperate and have undergone compliance checking out and plug-fests.

  • The IP design crew need to be experienced within the connectivity protocols and have the analog/blended sign design capabilities to design within the latest deep sub-micron technologies.

  • The IP dealer assisting the interconnect demands of today must even have a roadmap for future necessities and wide coverage of fabrication applied sciences.

  • World-vast support should be accessible during tape-out and after the SoC comes again.

  • concerning the author

    Navraj Nandra is Director, advertising combined-sign IP at Synopsys.

    Acknowledgements

    Contributions to this paper have been made by way of Gervais Fong, David Wallace, Joe Guiliano, Bob Lefferts (Synopsys) Boris Litinsky (Juniper Networks)




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