RSA 050-SEPRODLP-01 : RSA Certified SE Professional in Data Loss Protection Exam
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RSA Loss Practice Test
Arthur Low, Crack SemiconductorChelsea, Canada
this text reports the heritage of key advances in ICs and EDA tools. The standard theme offered listed here for the motive force of know-how innovation is the requirement to increase probably the most advanced microprocessor feasible. today, a comparatively cheap, excessive-price-added business mannequin can successfully serve the market for IC subsystems licensed as highbrow property (silicon IP) within the variety of compilable source code. on the other hand, for bigger SoC designs, engineering budgets will also be shifted from the purchase of a comparatively small number of high-charge EDA tool licenses to open source EDA applied sciences that can also be run on huge compute-server farms. the two company fashions aren't theoretical, however simple. The author explains how his company (Crack Semiconductor) developed commercially successful cryptographic silicon IP the use of entirely open source EDA applied sciences and how one more enterprise (SiCortex) pushed the boundaries of IC design and open supply EDA tools by way of simulating and verifying a massively parallel supercomputer.
setting up SILICON IP WITH OPEN source tools
The electronic design automation (EDA) tool business is massive company, and commercial licenses are extremely high priced. Open specifications have pushed many proprietary EDA applied sciences to be publicly released as free/libre open source application (F/LOSS) and a few have become IEEE requirements. competition has partly given technique to collaboration and has led to these requisites. The construction course of vital EDA tools frequently now employs F/LOSS practices, which have overcome resistance to collaborative innovation between competing corporations. F/LOSS applied sciences are at the leading edge of main-side device-on-chip (SoC) design, now not just as a result of they're free, but additionally as a result of they are effective.
the first commercial integrated circuits (ICs), designed via hand, helped e-book manned space flight to the moon on the Apollo missions. during the past decade, silicon IP organizations have shown they're constrained best by means of their ideas, no longer through limited investment opportunities, and SoC organisations have shown they could significantly cut back costs whereas innovating on the construction of the largest new IC designs. This high-conclusion technology is made obtainable to startups as a result of open supply. It is no longer only for mega-companies.
“The complexity for minimal component prices has increased at a cost of roughly an element of two per year... [T]here isn't any reason to accept as true with it'll now not continue to be pretty much consistent for at the least 10 years... in all probability newly devised design automation strategies could translate from good judgment diagram to technological attention without any special engineering.”Gordon E. MooreElectronics, April 19, 1965
In 1965, Gordon E. Moore changed into Director of Fairchild Semiconductor's R&D laboratories and made his noted statement, as quoted above, that could become called "Moore's legislations". at the moment, ICs had been carefully coupled to rocket science (figuratively and actually), and microprocessors had no longer yet been invented. Fairchild changed into then busy providing the first commercial ICs for the Apollo guidance computing device. This desktop was used on the a success moon missions, and it helped carry Apollo 13 lower back home. lots of Fairchild ICs, containing most effective a NOR gate with three transistors each and every, have been used to build one equipment. it will take more than twenty years and billions of greenbacks value of commercial R&D to obtain Moore's prediction of EDA tools that could “translate from logic diagrams to technological attention without any particular engineering”.
In 1968, Gordon Moore and Robert Noyce based Intel, a basic Silicon Valley startup, which in 1971 produced the primary microprocessor (uP) design. this first microprocessor contained 2300 transistors. Intel uP transistor counts grew to 820 million in 35 years, a 2.07 times increase every two years. Moore's legislations was coined by means of Carver Mead, professor of VLSI design at Caltech, in reference to Moore's prediction of the boom fee of IC designs in his now-famous 1965 Electronics article.
through the mid-1980s, a extra effective option to common sense diagrams regarded: software-like hardware description languages (HDLs) that model concurrent good judgment circuit undertaking. the us Air force required the comprehensive good judgment useful description of a digital IC. This requirement ended in the open language specification called VHDL. Proprietary good judgment simulation know-how helped fuel the growth of the business IC business. As a company method to counter VHDL's beneficial properties in market share, the dominant language (Verilog) became later released to an impartial firm so it can be developed as an open specification. sarcastically, each VHDL and Verilog have turn into IEEE requisites managed by using the same firm, now known as Accellera.
Proprietary good judgment design and simulation device projects, for essentially 50 years, were supported inside vertically built-in mega-corporations, and that they, just like the tools, have prospered and withered. a number of EDA and IC startups flourished to turn into mega-businesses themselves, however many failed and quietly dwindled away. IC businesses (corresponding to Intel), telecommunications R&D labs (equivalent to Bell-Northern analysis, or BNR), and laptop giants (such as IBM and Digital gadget supplier, or DEC), all developed inside EDA tools to guide their own chip designs. Later, a strong EDA trade formed as engineers left tremendous businesses to beginning new enterprises.
in the next area, they discuss the emergence of the silicon IP business mannequin and the way proprietary equipment have given a way to F/LOSS equipment. in the closing section, they demonstrate that F/LOSS equipment can assist silicon IP company founders avoid dilution of their shares within the enterprise and loss of control earlier than the concept is turned into a vital innovation. they could additionally support the low-cost exchange-off of costly tool licenses versus computing elements. An illustration of every is given: F/LOSS equipment enabled the author to Excellerate commercially a success cryptographic silicon IP, and the extreme limits of IC design had been pushed by using simulating and verifying a hugely parallel supercomputer.
The Emergence of the Silicon IP enterprise mannequin
during this part, the development of the microprocessor is used as the commonplace design point. The silicon IP business mannequin is shown to have been preceded first through the vertically prepared, fabricating semiconductor enterprise. The fabless semiconductor enterprise outsourced IC fabrication and so required vastly smaller funding capital, however each and every enterprise class still designed everything "in-residence". Design teams had been large and demanding financial components required undertaking capital to be raised. At a critical moment, design tools enabled totally productive and a lot smaller design groups, and the microprocessor conception took a bounce forward with the introduction of the reduced instruction set compute (RISC) as a core of silicon IP that was licensed devoid of ever having been manufactured. This changed into adopted through the introduction of the programmable good judgment chip, and eventually, F/LOSS design tools that allow silicon IP startups to design, examine, and bring working IC designs with very nearly no capital investment beyond their intellectual contributions.
lengthy earlier than the silicon IP company mannequin emerged to fill the present market need, microprocessors had been designed via very big excessive-technology agencies. These corporations were often vertically integrated with the aid of necessity. This ended in the development of inside EDA technologies that predated equivalent business offerings. An advanced technology company owned its personal IC design and manufacturing strategies, and its interior device building courses were carefully coupled to those processes. Examples consist of IBM's "Einstimer" tool for checking if the chip indicators meet timing requirements and BNR's "Funsim" hardware design simulator.
The vertically built-in "semiconductor fabrication-oriented" enterprise mannequin was joined via the "fabless" semiconductor startup, which changed into enabled by using the availability of business EDA tools. The fabless semiconductor enterprise - evidently conceivable in the mid-Nineties - now may design the entire good judgment features required in an software-selected IC (ASIC), with out wanting a producing potential. The ASIC design may then be manufactured through a semiconductor foundry, called the "fab". but, relentlessly, IC designs have grown by Moore's law. it's now somewhat impractical for one company to design the entire logic functions in the chip, so the silicon IP market now materials a big ratio of the useful good judgment to an organization that integrates these subsystems on an SoC.
The classic IC microprocessor that become designed and manufactured through one company began to face competition in the Nineteen Nineties. ARM Ltd., which started as Acorn computers and became joined later by using Apple and VLSI technologies, developed the silicon IP business mannequin with the aid of introducing a small, but potent reduced guide set laptop (RISC) design to be licensed to different agencies that might embed the silicon IP into their IC design. Embedded RISC processors are used in just about all of modern-day scorching products, reminiscent of wise telephones and drugs. through 2008, over 10 billion ARM processors had been licensed. ARM's preliminary success as a silicon IP dealer in the microprocessor market validated that big industrial components aren't required for the silicon IP business mannequin. ARM proved that small design groups - even one individual - can produce beneficial processor designs as silicon IP.
A remaining plank within the silicon IP business model platform is the container programmable gate array (FPGA). The FPGA has allowed Moore's prophetic demand "design automation tactics [that] could translate from good judgment diagram to technological consciousness without any particular engineering" to be realized. both leading FPGA providers, Xilinx and Altera, provide economical or free equipment to automatically convert HDL source code to a tool-certain technology, area it on the pre-manufactured chip, and wire up the add-ons in minutes.
From Proprietary EDA equipment to F/LOSS solutions
in the beginning, silicon IP carriers had little option however to acquire expensive EDA device licenses the place each and every simulator might charge, as an instance, $25,000. This need continually forced the founders to hand over fairness to fund their improvements. Now with F/LOSS equipment for EDA, innovators can Excellerate their advanced silicon IP, and with FPGA technology, the silicon IP seller can let a potential consumer consider the IP of their personal design for terribly reasonably priced and chance.
The emergence of an F/LOSS suite of EDA tools for the entrance-conclusion logic design and verification has followed a fascinating course. during this area, the requirement for a technology that would allow application and hardware to be modeled and simulated is described. Two problems drove this stream to open supply EDA tools; one is technical and the different is company-oriented, regarding how competitors can collaborate. As a secondary effect, open supply applied sciences have enabled the most economical silicon IP startup as a manageable enterprise to supply both real designs and models to permit faster and higher-fine solutions. These technologies have liberated the silicon IP company mannequin from its dependence on enormously diluting project capital.
The technical issue to be solved will also be summarized by means of the following query: How can complicated microprocessor designs execute utility, in view that the interplay between utility and hardware ought to be neatly understood before the design is committed to silicon? This conception is referred to as co-simulation. The competitor's difficulty changed into to check how the enterprise can earnings if it shares its advanced EDA tool innovations with its competitor.
within the 1990s, the need for a co-simulation know-how lead DEC to develop Verilator - discussed in more desirable element below - purely for DEC's inner use. DEC's misfortune has result in other's fortune, as a result of Verilator is now the leading F/LOSS device for the silicon IP startup on a micro-finances. The calls for for even greater equipment-level co-simulation and modeling expertise resulted in SystemC as a collaborative effort between EDA corporations. Verilator and SystemC form the "killer app" for silicon IP startups.
excessive engineering challenges confront main-area IC development projects. inner innovation is often the most effective alternative to beat a technical limitation of a commercial EDA device. although, with entry to the supply code, a characteristic can also be brought or a bug may also be fixed directly.
The microprocessor IC is customarily so complicated that many simulations of its operation are required to check the design. necessities ended in capabilities that frequently might simplest be developed by means of inside EDA device construction groups working closely with the processor designers. Most vertically built-in organizations funded (and many continue to fund) interior EDA tool development and had proprietary design flows. industry standardization was viewed by way of main-side companies, commonly correctly, as imposing a step down in skill. Processor designs were commonly way more advanced than the logic devices that may well be designed and manufactured with industrial EDA equipment, and that they often pushed those equipment previous the breaking aspect. Arguably, the internal equipment of Intel, IBM, DEC, and BNR have been the crown jewels of each and every employer. but this ordinary observe of inside development also resulted in wasteful duplication and resistance to external concepts and improvements, which were neglected since the had been "now not invented here".
Many organizations today are picking out to collaborate with their competition on the building of primary technologies by means of supporting F/LOSS EDA initiatives. besides the fact that children, here is not so within the case of DEC in opposition t Intel.
Intel is now a dominant microprocessor IC business, however many companies vied for the place, together with IBM, AMD, and DEC. Intel handiest emerged because the dominant processor dealer after it began its “Wintel” collaboration with Microsoft. DEC's innovation for its Alpha processor is a superb case study. To determine the Alpha, DEC developed the device referred to as Verilator beginning in 1994. The requirement was to co-simulate C (application code) and Verilog (hardware code) collectively. Verilog became “verilated” to C for DEC's Alpha uP assignment and then compiled with a C compiler. In 1998, nearing the end of a long run, DEC publicly launched the source code for Verilator earlier than the business became bought to Compaq. for the reason that 2001, Verilator has been maintained by way of Wilson Snyder.
Processor design is now more complicated than ever, and silicon IP can not be developed following the writing of unique design necessities for each software and hardware. This takes too lengthy and correct designs emerge from universal, brief new release cycles using first models and then extra particular modules. So, leading edge EDA groups determined to collaborate via forming the Open SystemC Initiative. by means of taking part in the specification of the SystemC language and its later extensions, these companies certain that a strong market for their cost-added co-simulation and modeling design equipment would exist.
Silicon IP Developed With Verilator and SystemC
The creator's company, Crack Semiconductor, lately licensed to a huge European client an RSA public key cryptographic protection processor to speed up banking safety transactions. Crack Semiconductor's RSA processor optimally multiplies numbers that are giant: 1024-bits and bigger. The IP changed into developed in Verilog and become verilated to SystemC, and then became compiled with G++ for simulation. A SystemC test environment generated random numbers, that have been used as a groundwork for an exterior characteristic call to pre-compute equipment constants and the expected effects using GNU bc, an arbitrary precision calculator language. The SystemC look at various then read the anticipated results from a file, programmed the digital processor, and completed the simulation of the verilated RSA processor. right through construction, when consequences had been flawed, bc scripts were written to compute intermediate outcomes to examine towards the values generated via the 32-bit multiplier, or at another selected observation point in the processor. There are no business equipment available to try this sort of “really expert engineering”. at last, for delivery to the customer, free synthesis equipment offered by using Xilinx have been used to convert the tender IP core to a technology-selected format used with the aid of the client.
expertise innovation in IC design methodologies frequently triggers new concepts for F/LOSS EDA tools for you to guide the next technology of IC designs. Wilson Snyder turned into a member of the building crew that designed the 972-node parallel SiCortex supercomputer. The 200 million transistor SiCortex chip incorporates sixty four-bit RISC processors that represents one “node” in the supercomputer, and turned into developed using the identical simple technology used with the aid of Crack Semiconductor. The SiCortex group exploited all manner of open supply technologies to permit up to 4 hundred Linux compute servers to run simulations in parallel and document what aspects of the verify plan have been coated. This new open supply technology is called CovVise. CovVise isn't just one technology, but really leverages a large choice of F/LOSS applied sciences often known as LAMP (Linux working gadget, Apache net server, MySQL database, and Perl/php scripting language). A industrial Verilog simulator license has an inventory fee around $25,000, so economically, Verilator, SystemC, and CovVise represents a compelling for significant IC design groups
On the forty sixth anniversary of Gordon E. Moore's seminal paper in digital, F/LOSS EDA tools permit common sense descriptions to be technologically realized with none particular engineering, as Moore estimated. entrance-end design engineering of silicon IP nevertheless requires extraordinarily really good engineering issue-solving efforts, and usually industrial tools do not utterly handle the problems that come up. Engineers at the leading edge of technological development routinely must invent new design and verification equipment, and F/LOSS is indispensable in this effort.
All method of enterprise models are receptive to F/LOSS EDA equipment. From silicon IP startups with micro-budgets to significant companies like NXP (Philips Semiconductor), many corporations use these equipment today. They do shop funds through the use of F/LOSS, but they do not use them just as a result of they're free of monetary can charge. They use them as a result of they are constructive. From DEC to SiCortex and Crack Semiconductor, open supply Verilator, combined with IEEE common SystemC and SystemPerl, offers compelling cost for silicon IP startups.