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IBM v1 Practice Test

constructing a Reusable IP Platform inside a equipment-on-Chip Design Framework centered in opposition t an educational R&D atmosphere | 000-N36 test Braindumps and test Cram

by way of Brendan Mullane and Ciaran MacNamee,Circuits and system analysis Centre (CSRC),school of Limerick, Limerick, eire

abstract:

A key challenge facing the semiconductor business is to mix highbrow Property (IP) from a number of sources promptly and effectively. Design times are always pressurized by time to market necessities and lengthening complexity. Industrial practices for developing device-on-Chip (SoC) IP have developed below these pressures, but applying these practices in an tutorial environment gifts extra challenges. The theory for developing a framework for generating IP changed into in response to this reuse revolution and the advantages it brings to R&D. The capacity to design high excellent IP and to allow work practices for reuse methodology helps to obtain working SoCs in a timely and efficient manner. This paper describes a methodology for imposing IP reuse practices ideal to an tutorial environment.

1. Introduction

various elements are crucial for efficient IP use, flexibility of integration, better ease-of-use, minimized can charge, and good work practices for developing IP. This paper is in line with specific work developing an ASIC the usage of 0.35ìm method expertise. The structure in this IC is comparable to SoC designs that use an eight-bit CPU and linked peripherals. it is proven that the framework for IP development based throughout this mission can ensure a success deployment of each present and new designs in future tasks.

The latest style in SoC design is to utilize latest IP as a good deal as viable. IP within the variety of CPUs, DSPs and controllers, are being reused in new IC initiatives at semiconductor programs design residences. Engineering teams now design chips with tens of millions of gates in below a 12 months. just recently, such productivity would were inconceivable, even unthinkable devoid of hardware IP reuse. Most tutorial environments don't have the components and infrastructure to allow such engineering potential, although the underlying principles of reuse can be utilized to permit greater positive IP era and potential retention for constructive R&D.

This paper introduces a collection of instructions and a methodology used to be certain a consistent method to designing IP and to enable for reuse of these modules in future initiatives. the first stage became to examine top of the line industrial follow. Work describing the ASIC development cycle and its have an effect on on IP generation was performed. a group of necessities for ensuring IP first-rate and ease of integration became also organized. A key objective changed into to be sure talents can be retained in the school centre to keep in mind expected graduate turnover.

2. IP Reuse Framework in CSRC

A assessment of the commonplace concerns in design use and reuse become initiated [1]. a number of IP necessities had been reviewed and these included Freescale’s Semiconductor Reuse average [2], VSI Alliance’s set of requirements for setting up SoCs [3] and OpenMORE [4]. IP reuse may on no account have happened devoid of requisites or devoid of the underlying infrastructure [5]. Design and verification reuse, a fact of existence these days for most SoC designs, ensures the productivity hole is kept manageable[6]. Design reuse considered an easy theory that will also be effectively adopted, has persevered to be challenging in follow. issues exist in getting engineers to have faith that reusable IP will work every time it is used in an IC. offering IP help features and adoption of a correct verification process develops this have confidence.

2.1 SoC structure and Infrastructure

The intention of this venture turned into to establish a design methodology for generating IP. The methodology thinking architectural selections and selection of design-flows for IP construction accompanied by using the prerequisite IC design tools. undertaking standards such because the SoC architecture, third-birthday party core use, in-apartment IP construction and the gadget bus interface were all considered before the IC architecture became concluded and the peripheral integration became performed. The primary SoC architectural diagram is proven in determine 1 and the finished chip changed into taken through verification and the back-end degrees of synthesis, layout, static timing analysis and final design rule checking.

determine 1: SoC Design structure

the following key choices were made in relation to the IP guide constitution.

2.1.1 Peripheral Bus Interface

The preference of a standard SoC device bus for connecting the CPU to the system peripherals was essential to the goals of this venture. using a standardized bus architecture is elementary to establishing reusable IP. a considerable number of bus requirements have been investigated for the needs of the CSRC IC projects. The 8051 CPU changed into used during this design and although the interior particular function Register (SFR) bus become considered, the authors wished to employ a typical bus design to be reused in other IC implementations.

many of the major IC and IP groups base their IP portfolio construction round a single SoC bus structure. Semiconductor organizations comparable to ARM and LSI common sense use the open supply AMBATM [7] bus general. IBM makes use of its personal proprietary CoreConnectTM [8] bus commonplace. The OpenCores initiative uses the WishboneTM [9] described bus interface. The authors observed that the AMBA bus architecture changed into well supported amongst the IP seller neighborhood. This large acceptance arises from the availability of an open bus standard it's license free and smartly confirmed in current SoC designs. clients have a high diploma of self belief selecting IP that is considered dealer impartial. additionally, the AMBA bus is neatly supported by means of EDA companies offering verification guide. The AMBA bus become chosen because the bus interface for CSRC SoC initiatives for these causes.

The AMBA bus makes it possible for partitioning for modular designs[10]. Its methodology for embedded processor design encourages both a modular and first time right device design. It also accelerates product migration by using assisting module reuse. In particular, the AMBA APB bus specifies a versatile interface and small overhead help for low bandwidth peripherals. The IP design the usage of the AMBA interface is made simpler via partitioning the excessive-conclusion and low-conclusion instruments in the equipment and supports power productive designs. all of the peripherals in this design used the AMBA - advanced Peripheral Bus (APB) as the standardized interface. The CPU as a single bus grasp turned into interfaced to all of the peripherals by the use of an in-residence designed AMBA bridge interface.

The merits of the usage of a standard bus interface for core development are smartly documented [1, 10, 11]. A trial AMBA APB register module, proven in determine 2, turned into advantageous for demonstrating the desired interface design to postgraduates. The RTL code for this module helped the team to take into account the ideas of decent coding follow to encompass parameterization and confirmed the use of revision control for code changes and malicious program fixes. all the IP developed during this IC project may also be reused in another AMBA primarily based SoC purposes and this aids future product and platform construction

figure 2: pattern APB module

2.1.2 third birthday celebration Core Licensing

an extra big task was to designate an appropriate microcontroller for the project. The IP community become approached in regards to licensing of the CPU and debug cores. there have been a number of elements to licensing IP cores from an tutorial point of view. It was fundamental to be sure a licensing association turned into made the usage of a non-industrial analysis- licensing model. Many vendors have been most effective prepared to license their cores in accordance with a full industrial arrangement and the charges quoted have been past an academic research price range. Some vendors had been inclined to trust a reduced non-industrial license price with the re-introduction of full expenses supplied the IC proceeds to commercial utility. other IP carriers limited their set of deliverables to FPGA netlist implementation only. This restrained their option of third celebration CPU and debug cores. fortunately, some IP organizations had experience coping with academic instances and have been prepared to liberate IP deliverables and guide for non-commercial analysis undertaking at a decreased can charge. The leading author changed into able to perform a survey of relevant cores and got here to an agreement for the third celebration IP crucial for the SoC task.

2.1.3 Design Flows

The ASIC design flow and electronic Design Automation (EDA) device preference is an important component of an efficient IP framework. The alternative of equipment need to complement the design flows and help reusability of IP. The centre accesses tool sets provided as tutorial programmes from the semiconductor EDA corporations. The CSRC additionally has access to commonplace EDA tools by way of the Europractice[12] application carrier scheme. Their FPGA and Digital design flows were drawn up around the availability of those tools and to plan the SoC IP building and integration. These flows have been beneficial in identifying the distinct ranges concerned within the building of IP and SoC designs. moreover the digital design flow, a stream for FPGA prototyping became also brought. The FPGA building makes it possible for for an inexpensive design validation platform and provides confidence by way of ensuring proper behavior earlier than ultimate tape-out.

2.1.three.1 Digital IC Design circulate

The digital design follows the basic ASIC implementation route. a couple of semiconductor business web sites and technical paper searches revealed the standard design circulate that exists for digital ASIC design [13], [14].

determine 3: Digital IC design stream

The design movement and tools choice as drawn up in figure three have been tailored to device availability and the option of IC strategies provided via Europractice.

2.1.3.2 FPGA Design circulation

The FPGA stream in determine four is terribly comparable to the digital IC design movement, however the design tools to put in force and software a FPGA design are different. The assignment used the Xilinx design kits and equipment made purchasable by means of the Xilinx college Programme. They used Xilinx Spartan 2 and 3 boards to implement the digital design elements. The Xilinx ISE webpack is a set of tools that takes Verilog RTL code and runs it via synthesis, genuine layout to device configuration. The closing bit file can then be downloaded to program the FPGA device to investigate the practical habits of the digital design. FPGA verification thoughts and their importance in design validation and reuse are mentioned later.

determine 4: FPGA Design move

2.2 CAD Infrastructure

The CAD infrastructure became more advantageous to perform SoC construction in the centre. The usual constitution protected three low-grade UNIX servers for working the IC design equipment and preserving task records. A plan changed into initiated to Excellerate the IT hardware needs. each and every of the person PCs were put in with VMware Linux, permitting clients to maintain their home windows OS but extra importantly every pc might use its personal CPU processing vigor with Linux to deliver stronger efficiency. Two high power Linux mainframes, received for holding the venture databases have been additionally utilized as license servers for the supported EDA equipment. the new set-up provides the efficiency necessities to carry out IC R&D inside the CSRC centre.

an extra step turned into opting for the EDA equipment crucial for IP development. tools for verification and making certain fine of RTL code have been not in region. youngsters using their Europractice membership, the centre had entry to general EDA tools at a decreased cost. tools equivalent to ModelSim for RTL verification and Leda for RTL evaluation had been received. The existing edition of Design Compiler become additionally upgraded in keeping with trade requirements.

3. Design Methodology and IP reuse Implementation

software of reuse can pay off when it comes to building charge and time-to-market. This part summarizes the building milestones for a standard IP design. Defining the stream and linked design reports helps ensure a repeatable, excessive great, and reusable block of peripheral IP. another advantage of a documented movement is that other design groups can use this system to advance IP in an identical manner; guaranteeing IP is constant in its implementation, integration move, deliverables, and normal best.

three.1 development Milestones

IP/SoC design milestones are critical to the delivery of working silicon and achieving a ‘right first time’ coverage. These milestones are markers positioned down all the way through the development part to manipulate and measure the design activity and development. These markers indicate studies taking place right through the essential tiers of the design phase from delivery to conclusion. Milestones take place on the natural progression of the challenge. figure 5 and table 1 describe the signal-off milestones to encompass all major design studies.

figure 5: IP construction Milestones

table 1: IP building tiers

stageReview Description FSR functional Spec review functional specification is finished, particulars on effort estimation, work breakdown constitution and schedule. DSR Design start review Design delivery, working towards, RTL coding & synthesis guidelinesTPR check Plan assessment finished specification of verification ambiance, look at various instances, bus-models, transactors. RCR RTL Code evaluation RTL worm fixes identified via exhaustive verification & RTL Lint/code checking TLR Trial design evaluate set up floorplan and perform P&R. Floorplan based on module connectivity, get to the bottom of congestion and timing –look at clocking FVR last Verification review high precedence testing completed. widely used bugs within the RTL are mounted. coverage analyzed. Low priority trying out good enough. FDR closing Design evaluation assessment integrity exams (DRC, LVS) STA, check Vectors and closing gate-degree verification with complete design timing.

3.2 undertaking Database structure

A standardized listing constitution is a must have for IP reusability. a good and simple to use database constitution ensures compatibility and consistency of peripheral design. IP construction comprises specification, coding and verification as key design degrees. consequently, many assist file formats are required. IP upkeep is also a key concept in IP reuse. The ability to log and hold music of design adjustments is vital to the normal satisfactory of the design. determine 6 suggests the CSRC listing constitution to assist the IP construction levels.

determine 6: usual CSRC listing Database

three.3. Reuse guidelines

three.three.1 Specification experiences

The design reports are giant when it comes to generating a framework for IP development and reuse. These stories help documentation and ensure good design practices.

three.3.2 functional Specification

This doc offers an in depth purposeful description of the module and is written in advance of the IP construction. The FSR evaluation takes location to make certain all facets of the peripheral performance are lined. The specification should be used to start the design and RTL coding. The useful specification needs to be up-to-date for that reason with any additional aspects necessities. The CSRC makes use of a draft template doc as a tenet for producing purposeful block and IC design requirements.

3.three.3 RTL Coding and analysis

RTL construction contains coding the peripheral in a hardware description language reminiscent of Verilog or VHDL. Verilog RTL became used and a set of coding instructions for the IP technology was issued. This set of coding principles ensures consistency, coding trend exceptional and offers for superior preservation. The RCR is a high degree overview of the RTL code to be sure it's stylistically relevant and maintainable. The intent is to double-investigate the code pleasant. The foundation for this evaluate is the RCR guidelines. RTL evaluation is performed using Leda for crosschecking RTL code rules towards the Reuse Methodology manual (RMM). initial FPGA/IC synthesis can also be used to highlight any RTL considerations with reference to synthesis.

3.3.four Revision control

Revision manage is indispensable to the theory of design reuse and ensures essential suggestions is not lost right through the design section. Revision control and file management is principally crucial all through RTL coding as any code misplaced all over this stage can critically affect the ordinary design timeline. To support manipulate files, engineers use supply control management techniques. These are typically bundled with the Linux working techniques or available from GNU (RCS, CVS, Subversion). These code administration programs provide an entire background of every file as separate models.

3.3.5 malicious program upkeep

dealing with bugs is an important consideration for any design framework. it's commonplace to find functional irregularities in the design and their prevalence does not reflect the talents of hardware designers. once an issue is identified, it must be resolved. All design teams want a way for tracking considerations and making certain their resolution. The authors proposed preserving a computer virus document for any design connected issues.

three.four Verification and Validation ambiance

The verification part is vital to offering first time working silicon. Their verification methodology uses a twin tune strategy. Verification happens at the module stage and also at the SoC equipment level. The Module Verification ambiance (MVE) functionally validates the core and ensures all design traits have been comprehensively demonstrated. The SoC Verification ambiance (SVE) assessments the cores’ habits on the device stage and in specific checks the connectivity between the core interfaces. An FPGA/ASIC design verification method turned into used to validate the undertaking on the device SoC stage.

three.four.1 Module Verification atmosphere (MVE)

an important part of the MVE became the technology of the APB Bus functional model (BFM) to generate the practical habits of the gadget bus. the entire peripherals were in accordance with this standardized bus architecture and this enabled the use of a general model to test the bus interface and registers contained in the peripherals. This model additional provided a simple to use test atmosphere. The diagram in determine 7 illustrates this. The BFM utilized Verilog projects for read/write accesses, together with wait state manage and became reused in all of the peripheral check environments. The BFM changed into beneficial for running tests to achieve confidence in the practical habits and for targeting excessive code coverage.

figure 7: APB Bus purposeful mannequin

3.4.2 SoC Verification ambiance (SVE)

The SVE consisted of a separate however equivalent test solution for FPGA prototyping and the ASIC gadget level verification. The FPGA solution changed into constructive for mapping the complete SoC RTL code to consist of the CPU, debugger and the entire peripherals onto a FPGA. determine eight illustrates the basic structure implemented onto the FPGA equipment.

figure eight: FPGA Prototype Validation

The CPU and different main peripherals are connected together as a single platform and assessments were developed in R8051 CPU core software code to operate the peripheral exams. The ASIC verification atmosphere is comparable to the FPGA look at various bed, apart from in this case all checks were run the usage of RTL and procedure particular gate-degree stimulations. each and every of the peripheral firmware exams developed for the FPGA prototyping were reused at ASIC gadget level.

4. effects and Conclusions

The venture goal was to put into effect a SoC design framework for the start of reusable IP. The selected normal system bus aided the construction of plug and play peripherals that will also be reused in lots of different SoC purposes. The building of the 8051 CPU exterior facts bus to system bus-bridge offered for a standardized interface and simplified the peripheral construction.

The design flows of Figures 4 and 5 were adopted to be certain a consistent design approach for the building and equivalent assist for business regular EDA equipment. The directory constitution as explained in section three.2 turned into also essential for associating data with each stage of the IC building and retaining a smartly-managed database. each and every of the implemented IP blocks follows this conventional database structure and this ensures reusability going ahead. Design studies ensured self belief and great of the IP block design. The Verilog code changed into reviewed to be certain revision control and RTL coding guidelines were adhered to. an analogous evaluation was carried out to be certain the verification environments at module and equipment degree have been applicable to check the performance of these designs. The RTL became validated on a FPGA machine and tests had been carried out on the system level to verify the peripherals related to the 8051 CPU.

The IP framework as discussed in this paper is suitable for implementation in an tutorial centre wishing to perform a reusable IP programme. this technique and reuse strategies are established in trade, but as a result of funding and useful resource constraints, may also now not all the time be effortless to deploy in an tutorial atmosphere. This paper discusses the implementation of IP development for reduce bandwidth peripherals; even so the underlying ideas of IP use and reuse are the identical.

four.1 academic Centre Specifics

body of workers requirements for research are finally resourced from graduates pursing MEng and PhD levels. inside the CSRC, group of workers and tutorial researchers are chargeable for main tasks and mentoring college students. The graduates want talents development to deliver them as much as velocity and having a structured development methodology makes it possible for deliverables to be met in a well timed fashion. The advantages of IP expertise retention became another reason for introducing the IP building framework, as work generated on tasks performed in the past would had been elaborate to progress as soon as postgraduates had accomplished their research degrees. This changed into a vital subject to unravel, as helpful assignment work performed during the past can also have been unnecessarily misplaced.

4.2. Future options

The cores may be further more desirable by way of featuring a system C or C mannequin as part of the developmental ranges to additional the stage of abstraction and to speed up design verification and utility development.

SystemVerilog is a hardware design and verification language with advanced aspects supposed to aid clients enhance reusable, transaction-level, insurance-driven testbenches. suggestions equivalent to fact primarily based Verification (ABV) can be applied to the bus protocol to monitor pin activity and the application of coverage-driven exams add self assurance in working silicon and provide an exhaustive trying out ambiance. These elements introduce ideas of verification reuse.

Design for examine (DfT) is commonly excluded from the design flow in an educational environment. DfT is a really vital function crucial for IP reuse. The IEEE 1500 usual for Embedded Core verify (SECT) specifies a core wrapper design to accommodate DfT aspects. This IEEE 1500 compliant wrapper design could provide a valuable extension to the current IP development stages.

5. Acknowledgements

The authors renowned the aid of the Circuits and techniques research Centre (CSRC) inside the digital and computer Engineering (ECE) Dept. at the institution of Limerick.

6. References

[1] Australian Microelectronics network, "IP design and Re-use," Jun, 2005.

[2] Freescale Semiconductor, "Semiconductor Reuse normal v3.2," Feb, 2005.

[3] VSIA Alliance, "VSIA structure doc v1.0," Mar, 1997.

[4] P. Bricard, Jean-Pierre Gukguen, "applying the OpenMORE evaluation program for IP Cores," in ISQED 2000: Synopsys, Mentor snap shots, March, 2000.

[5] J. Shandle, G. Martin, "Making embedded software reusable for SoCs," EETimes, Jan, 2002.

[6] J. Bergeron, "Writing Testbenches - practical Verificaton of HDL fashions", Kluwer academic Publishers, 2003.

[7] ARM, "AMBA™ Specification (Rev 2.0)," ARM LTD, may 1999.

[8] IBM. CoreConnect Bus. architecture, "http://www-03.ibm.com/chips/items/coreconnect/."

[9] R. Herveille, "WISHBONE gadget-on-Chip (SoC) Interconnection structure for transportable IP Cores," OpenCores organization, Sep, 2002.

[10] D. Flynn, "AMBA: Enabling Reusable On-Chip Designs," IEEE Micro, vol. 17, 1997.

[11] M. Kaskowitz, "flexible, necessities-based IP key," EETimes, Dec, 2002.

[12] Europractice, "http://www.msc.rl.ac.uk/europractice,"

[13] QualCore common sense, "QualCore SoC movement."

[14] V. P. Nelson, "VLSI/FPGA Design and check CAD tool flow in Mentor portraits," Feb 15, 2006.


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