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establishing a Reusable IP Platform within a gadget-on-Chip Design Framework centered against an academic R&D environment | 000-M73 Questions and Answers and test dumps

by means of Brendan Mullane and Ciaran MacNamee,Circuits and device research Centre (CSRC),university of Limerick, Limerick, ireland

abstract:

A key problem dealing with the semiconductor trade is to combine intellectual Property (IP) from a considerable number of sources instantly and effectively. Design times are invariably pressurized by using time to market requirements and extending complexity. Industrial practices for constructing device-on-Chip (SoC) IP have advanced under these pressures, but applying these practices in an tutorial environment items additional challenges. The concept for setting up a framework for producing IP turned into in response to this reuse revolution and the merits it brings to R&D. The skill to design high quality IP and to enable work practices for reuse methodology helps to achieve working SoCs in a timely and effective method. This paper describes a methodology for implementing IP reuse practices suited to an educational environment.

1. Introduction

a lot of components are vital for effective IP use, flexibility of integration, stronger ease-of-use, minimized cost, and first rate work practices for setting up IP. This paper is in accordance with precise work developing an ASIC the usage of 0.35ìm manner technology. The structure during this IC is comparable to SoC designs that use an 8-bit CPU and associated peripherals. it is proven that the framework for IP construction established throughout this undertaking can be sure successful deployment of each existing and new designs in future initiatives.

The present trend in SoC design is to utilize current IP as a whole lot as feasible. IP within the kind of CPUs, DSPs and controllers, are being reused in new IC initiatives at semiconductor methods design homes. Engineering groups now design chips with thousands and thousands of gates in below a year. just recently, such productivity would have been unattainable, even unthinkable without hardware IP reuse. Most educational environments wouldn't have the elements and infrastructure to permit such engineering capacity, besides the fact that children the underlying ideas of reuse will also be applied to allow greater effective IP era and potential retention for advantageous R&D.

This paper introduces a group of instructions and a methodology used to be sure a constant approach to designing IP and to allow for reuse of these modules in future initiatives. the first stage changed into to investigate optimum industrial practice. Work describing the ASIC building cycle and its affect on IP technology became performed. a group of necessities for ensuring IP first-class and ease of integration become additionally organized. A key aim was to make sure talents may be retained in the college centre to take note of anticipated graduate turnover.

2. IP Reuse Framework in CSRC

A evaluate of the general considerations in design use and reuse became initiated [1]. various IP specifications were reviewed and these protected Freescale’s Semiconductor Reuse common [2], VSI Alliance’s set of specifications for developing SoCs [3] and OpenMORE [4]. IP reuse could not ever have came about without specifications or with out the underlying infrastructure [5]. Design and verification reuse, a reality of existence these days for most SoC designs, ensures the productivity hole is saved manageable[6]. Design reuse regarded a simple concept that can be with ease adopted, has continued to be troublesome in apply. complications exist in getting engineers to have faith that reusable IP will work each time it's used in an IC. proposing IP assist features and adoption of a proper verification process develops this have confidence.

2.1 SoC architecture and Infrastructure

The aim of this project became to establish a design methodology for generating IP. The methodology thinking architectural choices and choice of design-flows for IP building accompanied by using the prerequisite IC design equipment. mission standards such because the SoC architecture, third-birthday party core use, in-condo IP development and the equipment bus interface were all regarded earlier than the IC structure turned into concluded and the peripheral integration was conducted. The basic SoC architectural diagram is proven in determine 1 and the finished chip changed into taken through verification and the back-end stages of synthesis, design, static timing analysis and final design rule checking.

figure 1: SoC Design architecture

here key selections had been made in relation to the IP aid structure.

2.1.1 Peripheral Bus Interface

The selection of a common SoC device bus for connecting the CPU to the equipment peripherals changed into crucial to the pursuits of this venture. the usage of a standardized bus architecture is basic to developing reusable IP. quite a lot of bus standards were investigated for the needs of the CSRC IC initiatives. The 8051 CPU was used during this design and however the inner particular characteristic Register (SFR) bus become considered, the authors wished to make use of a common bus design to be reused in other IC implementations.

lots of the important IC and IP companies base their IP portfolio building round a single SoC bus structure. Semiconductor businesses such as ARM and LSI good judgment use the open supply AMBATM [7] bus usual. IBM makes use of its personal proprietary CoreConnectTM [8] bus ordinary. The OpenCores initiative uses the WishboneTM [9] described bus interface. The authors accompanied that the AMBA bus structure become neatly supported amongst the IP dealer group. This large acceptance arises from the supply of an open bus general that is license free and well confirmed in latest SoC designs. clients have a excessive diploma of self belief determining IP this is considered provider unbiased. additionally, the AMBA bus is neatly supported via EDA agencies offering verification guide. The AMBA bus was chosen because the bus interface for CSRC SoC tasks for these reasons.

The AMBA bus enables partitioning for modular designs[10]. Its methodology for embedded processor design encourages each a modular and first time correct gadget design. It additionally quickens product migration through assisting module reuse. In specific, the AMBA APB bus specifies a versatile interface and small overhead assist for low bandwidth peripherals. The IP design using the AMBA interface is made less difficult by partitioning the excessive-conclusion and low-conclusion devices in the equipment and supports power productive designs. the entire peripherals in this design used the AMBA - superior Peripheral Bus (APB) because the standardized interface. The CPU as a single bus master changed into interfaced to all the peripherals by the use of an in-condominium designed AMBA bridge interface.

The benefits of the use of a typical bus interface for core construction are well documented [1, 10, 11]. A demo AMBA APB register module, shown in determine 2, was constructive for demonstrating the preferred interface design to postgraduates. The RTL code for this module helped the team to take into account the principles of first rate coding apply to encompass parameterization and established the use of revision handle for code alterations and trojan horse fixes. the entire IP developed in this IC project will also be reused in some other AMBA based SoC applications and this aids future product and platform development

figure 2: demo APB module

2.1.2 third birthday party Core Licensing

an extra large project became to designate a suitable microcontroller for the assignment. The IP community changed into approached with reference to licensing of the CPU and debug cores. there were a couple of points to licensing IP cores from an educational point of view. It changed into simple to be certain a licensing association changed into made using a non-industrial analysis- licensing mannequin. Many providers have been simplest prepared to license their cores in line with a full business association and the fees quoted had been beyond an educational research price range. Some providers had been willing to agree with a decreased non-commercial license fee with the re-introduction of full costs offered the IC proceeds to business application. different IP carriers limited their set of deliverables to FPGA netlist implementation simplest. This confined their option of 3rd celebration CPU and debug cores. happily, some IP companies had adventure dealing with tutorial cases and have been prepared to liberate IP deliverables and guide for non-industrial analysis activity at a decreased can charge. The leading author became able to perform a survey of appropriate cores and got here to an settlement for the 3rd party IP essential for the SoC project.

2.1.3 Design Flows

The ASIC design stream and digital Design Automation (EDA) tool selection is an important part of an efficient IP framework. The option of equipment should complement the design flows and support reusability of IP. The centre accesses tool units provided as tutorial programmes from the semiconductor EDA businesses. The CSRC also has entry to everyday EDA equipment via the Europractice[12] utility carrier scheme. Their FPGA and Digital design flows have been drawn up across the availability of those equipment and to devise the SoC IP building and integration. These flows had been helpful in determining the distinctive ranges thinking in the building of IP and SoC designs. apart from the digital design circulate, a move for FPGA prototyping turned into also added. The FPGA development permits for a reasonable design validation platform and provides self belief with the aid of guaranteeing correct habits earlier than last tape-out.

2.1.three.1 Digital IC Design flow

The digital design follows the classic ASIC implementation route. a number of semiconductor business web sites and technical paper searches printed the average design move that exists for digital ASIC design [13], [14].

determine three: Digital IC design stream

The design flow and tools preference as drawn up in figure three were tailored to tool availability and the alternative of IC tactics supplied via Europractice.

2.1.three.2 FPGA Design movement

The FPGA circulate in determine four is awfully corresponding to the digital IC design flow, but the design equipment to implement and application a FPGA design are diverse. The challenge used the Xilinx design kits and equipment made available via the Xilinx university Programme. They used Xilinx Spartan 2 and 3 boards to enforce the digital design facets. The Xilinx ISE webpack is a set of tools that takes Verilog RTL code and runs it through synthesis, genuine design to device configuration. The final bit file can then be downloaded to software the FPGA equipment to assess the practical behavior of the digital design. FPGA verification thoughts and their significance in design validation and reuse are mentioned later.

determine 4: FPGA Design circulate

2.2 CAD Infrastructure

The CAD infrastructure changed into better to carry out SoC construction inside the centre. The original structure included three low-grade UNIX servers for working the IC design tools and protecting assignment records. A plan changed into initiated to upgrade the IT hardware needs. each and every of the person PCs had been put in with VMware Linux, enabling users to retain their windows OS however more importantly every laptop could use its personal CPU processing vigour with Linux to bring stronger efficiency. Two high energy Linux mainframes, got for maintaining the assignment databases had been additionally utilized as license servers for the supported EDA equipment. the new set-up provides the efficiency requirements to perform IC R&D within the CSRC centre.

an additional step was choosing the EDA equipment necessary for IP development. tools for verification and making certain quality of RTL code have been no longer in region. although the use of their Europractice membership, the centre had access to general EDA tools at a reduced can charge. tools equivalent to ModelSim for RTL verification and Leda for RTL analysis have been acquired. The latest version of Design Compiler changed into additionally upgraded in response to industry requirements.

3. Design Methodology and IP reuse Implementation

application of reuse pays off when it comes to development cost and time-to-market. This part summarizes the construction milestones for a typical IP design. Defining the movement and associated design studies helps ensure a repeatable, excessive great, and reusable block of peripheral IP. yet another benefit of a documented flow is that other design businesses can use this methodology to strengthen IP in an identical means; making certain IP is constant in its implementation, integration move, deliverables, and usual nice.

three.1 construction Milestones

IP/SoC design milestones are critical to the delivery of working silicon and attaining a ‘right first time’ coverage. These milestones are markers placed down during the development phase to manipulate and measure the design exercise and development. These markers indicate experiences happening throughout the important levels of the design phase from delivery to conclusion. Milestones take vicinity at the herbal development of the venture. determine 5 and table 1 describe the sign-off milestones to encompass all major design reviews.

figure 5: IP building Milestones

table 1: IP building levels

stageReview Description FSR functional Spec assessment purposeful specification is complete, particulars on effort estimation, work breakdown structure and time table. DSR Design start review Design delivery, practising, RTL coding & synthesis checklistTPR verify Plan evaluation comprehensive specification of verification environment, verify instances, bus-fashions, transactors. RCR RTL Code overview RTL bug fixes identified through exhaustive verification & RTL Lint/code checking TLR Trial layout evaluation establish floorplan and perform P&R. Floorplan according to module connectivity, unravel congestion and timing –study clocking FVR closing Verification overview high precedence trying out achieved. accepted bugs within the RTL are fastened. coverage analyzed. Low precedence trying out adequate. FDR remaining Design evaluation overview integrity checks (DRC, LVS) STA, verify Vectors and final gate-stage verification with complete layout timing.

3.2 challenge Database constitution

A standardized listing constitution is a must have for IP reusability. an effective and easy to use database constitution ensures compatibility and consistency of peripheral design. IP development includes specification, coding and verification as key design tiers. due to this fact, many assist file formats are required. IP preservation is also a key theory in IP reuse. The potential to log and hold music of design adjustments is a must have to the normal satisfactory of the design. determine 6 indicates the CSRC listing constitution to assist the IP construction degrees.

figure 6: ordinary CSRC listing Database

3.three. Reuse instructions

three.3.1 Specification studies

The design experiences are tremendous when it comes to generating a framework for IP building and reuse. These reports aid documentation and confirm first rate design practices.

3.three.2 practical Specification

This document gives an in depth purposeful description of the module and is written prior to the IP building. The FSR review takes vicinity to make certain all aspects of the peripheral performance are coated. The specification could be used to start the design and RTL coding. The purposeful specification has to be up to date for that reason with any extra facets necessities. The CSRC makes use of a draft template doc as a suggestion for producing functional block and IC design requirements.

3.three.three RTL Coding and evaluation

RTL construction involves coding the peripheral in a hardware description language such as Verilog or VHDL. Verilog RTL became used and a group of coding guidelines for the IP technology was issued. This set of coding concepts ensures consistency, coding style pleasant and provides for improved preservation. The RCR is a high degree review of the RTL code to make certain it is stylistically correct and maintainable. The intent is to double-determine the code fine. The foundation for this evaluation is the RCR checklist. RTL evaluation is carried out using Leda for crosschecking RTL code guidelines towards the Reuse Methodology manual (RMM). initial FPGA/IC synthesis can even be used to highlight any RTL concerns with regard to synthesis.

three.three.4 Revision control

Revision handle is essential to the theory of design reuse and ensures essential advice is not misplaced all through the design part. Revision control and file management is notably crucial all the way through RTL coding as any code misplaced throughout this stage can seriously affect the average design timeline. To help manage information, engineers use source control management techniques. These are typically bundled with the Linux working programs or available from GNU (RCS, CVS, Subversion). These code administration systems provide an entire heritage of every file as separate types.

three.three.5 worm protection

coping with bugs is a vital consideration for any design framework. it's normal to find functional irregularities within the design and their prevalence doesn't reflect the competencies of hardware designers. once an issue is recognized, it must be resolved. All design teams want a way for tracking issues and making certain their decision. The authors proposed preserving a worm document for any design connected concerns.

3.4 Verification and Validation environment

The verification part is critical to offering first time working silicon. Their verification methodology uses a twin song method. Verification occurs on the module level and also on the SoC system degree. The Module Verification environment (MVE) functionally validates the core and ensures all design qualities have been comprehensively confirmed. The SoC Verification atmosphere (SVE) assessments the cores’ habits at the equipment level and in certain checks the connectivity between the core interfaces. An FPGA/ASIC design verification method become used to validate the mission at the equipment SoC degree.

3.4.1 Module Verification ambiance (MVE)

a vital a part of the MVE become the generation of the APB Bus purposeful model (BFM) to generate the purposeful conduct of the gadget bus. the entire peripherals were in line with this standardized bus architecture and this enabled the use of a standard model to examine the bus interface and registers contained inside the peripherals. This mannequin further offered an easy to make use of look at various atmosphere. The diagram in figure 7 illustrates this. The BFM utilized Verilog projects for study/write accesses, together with wait state manage and turned into reused in all the peripheral verify environments. The BFM turned into beneficial for running tests to achieve self assurance in the useful conduct and for targeting excessive code coverage.

determine 7: APB Bus purposeful model

three.four.2 SoC Verification environment (SVE)

The SVE consisted of a separate however identical verify solution for FPGA prototyping and the ASIC gadget degree verification. The FPGA solution changed into positive for mapping the comprehensive SoC RTL code to include the CPU, debugger and all the peripherals onto a FPGA. determine 8 illustrates the primary architecture implemented onto the FPGA gadget.

figure eight: FPGA Prototype Validation

The CPU and different main peripherals are related together as a single platform and assessments had been developed in R8051 CPU core software code to operate the peripheral assessments. The ASIC verification ambiance is akin to the FPGA look at various bed, except during this case all checks have been run using RTL and method particular gate-level stimulations. every of the peripheral firmware exams developed for the FPGA prototyping have been reused at ASIC equipment stage.

four. consequences and Conclusions

The venture goal was to put into effect a SoC design framework for the delivery of reusable IP. The selected regular device bus aided the building of plug and play peripherals that may also be reused in lots of other SoC purposes. The development of the 8051 CPU external data bus to gadget bus-bridge supplied for a standardized interface and simplified the peripheral construction.

The design flows of Figures four and 5 had been followed to make certain a consistent design method for the building and equal help for industry ordinary EDA equipment. The listing structure as defined in area 3.2 turned into also vital for associating data with each and every stage of the IC building and retaining a neatly-managed database. every of the carried out IP blocks follows this popular database structure and this ensures reusability going forward. Design reports ensured self assurance and high-quality of the IP block design. The Verilog code turned into reviewed to be sure revision handle and RTL coding instructions had been adhered to. an identical overview become performed to be sure the verification environments at module and device level have been applicable to test the functionality of those designs. The RTL turned into validated on a FPGA equipment and tests were performed on the system level to verify the peripherals related to the 8051 CPU.

The IP framework as discussed during this paper is appropriate for implementation in an educational centre wishing to perform a reusable IP programme. this technique and reuse suggestions are generic in industry, however as a result of funding and useful resource constraints, may also now not at all times be handy to install in an academic atmosphere. This paper discusses the implementation of IP development for decrease bandwidth peripherals; nonetheless the underlying principles of IP use and reuse are the identical.

four.1 educational Centre Specifics

workforce requirements for analysis are in the end resourced from graduates pursing MEng and PhD degrees. inside the CSRC, personnel and educational researchers are liable for main initiatives and mentoring students. The graduates need talents building to deliver them as much as pace and having a structured building methodology enables deliverables to be met in a timely vogue. The merits of IP advantage retention changed into another reason for introducing the IP construction framework, as work generated on tasks performed in the past would have been difficult to development once postgraduates had completed their analysis degrees. This turned into a vital subject to resolve, as positive mission work carried out in the past may were unnecessarily lost.

four.2. Future strategies

The cores can be extra greater by featuring a device C or C mannequin as a part of the developmental tiers to extra the stage of abstraction and to speed up design verification and utility construction.

SystemVerilog is a hardware design and verification language with advanced facets meant to help users Boost reusable, transaction-stage, insurance-pushed testbenches. techniques corresponding to fact based mostly Verification (ABV) can be utilized to the bus protocol to video display pin activity and the utility of insurance-driven assessments add confidence in working silicon and supply an exhaustive checking out atmosphere. These points introduce concepts of verification reuse.

Design for verify (DfT) is frequently excluded from the design movement in an tutorial ambiance. DfT is a very essential function needed for IP reuse. The IEEE 1500 standard for Embedded Core verify (SECT) specifies a core wrapper design to accommodate DfT elements. This IEEE 1500 compliant wrapper design could deliver a useful extension to the current IP building tiers.

5. Acknowledgements

The authors acknowledge the aid of the Circuits and methods research Centre (CSRC) in the digital and computer Engineering (ECE) Dept. at the university of Limerick.

6. References

[1] Australian Microelectronics network, "IP design and Re-use," Jun, 2005.

[2] Freescale Semiconductor, "Semiconductor Reuse typical v3.2," Feb, 2005.

[3] VSIA Alliance, "VSIA structure doc v1.0," Mar, 1997.

[4] P. Bricard, Jean-Pierre Gukguen, "making use of the OpenMORE assessment program for IP Cores," in ISQED 2000: Synopsys, Mentor images, March, 2000.

[5] J. Shandle, G. Martin, "Making embedded software reusable for SoCs," EETimes, Jan, 2002.

[6] J. Bergeron, "Writing Testbenches - functional Verificaton of HDL fashions", Kluwer educational Publishers, 2003.

[7] ARM, "AMBA™ Specification (Rev 2.0)," ARM LTD, may additionally 1999.

[8] IBM. CoreConnect Bus. architecture, "http://www-03.ibm.com/chips/products/coreconnect/."

[9] R. Herveille, "WISHBONE equipment-on-Chip (SoC) Interconnection architecture for transportable IP Cores," OpenCores corporation, Sep, 2002.

[10] D. Flynn, "AMBA: Enabling Reusable On-Chip Designs," IEEE Micro, vol. 17, 1997.

[11] M. Kaskowitz, "bendy, requirements-based IP key," EETimes, Dec, 2002.

[12] Europractice, "http://www.msc.rl.ac.uk/europractice,"

[13] QualCore good judgment, "QualCore SoC movement."

[14] V. P. Nelson, "VLSI/FPGA Design and test CAD tool movement in Mentor snap shots," Feb 15, 2006.


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